Re: 6502 to 7501/8501 converter

On 2018.06.18. 7:41, Jim Brain wrote:
> On 6/17/2018 2:42 PM, Hegedus, Istvan wrote:
>> I am missing here the GATE IN signal. That needs to be added just 
>> like I added it in FPGATED.  A transparent latch is needed to keep 
>> r_w_6502's previous state when GATE IN (MUX) is low. When MUX is high 
>> and AEC is not low r_w_7501 can be r_w_6502.
>> I would do the following (assuming gate_in is an input and 
>> r_w_latched is a register).
>>
>> reg r_w_latched;
>>
>> always @(gate_in,r_w_6502)
>>    begin
>>     if(gate_in)
>>         r_w_latched=r_w_6502;
>>    end
>>
>> assign r_w_7501 = (aec ? r_w_latched : 'bz);
>>
>> Istvan
>>
> I missed GATE_IN, so added as per your notes above.  compiler 
> complains bitterly about the use of a latch.  Would it be permissible 
> to do:
>
> always @(negedge gate_in)
>
> begin
>
>   if(!gate_in)
>
>     r_w_latched <= r_w_6502;
>
> end
>
> and then:
>
> always @(*)
>
> begin
>
> if(aec & gate_in)
>
>     r_w_7501 = r_w_6502;
>
> else if (aec & !gate_in)
>
>     r_w_7501 = r_w_latched;
>
> else
>
>     r_w_7501 = 'bz;
>
> end
>
> To skip the latch?
>
> -- 
> Jim Brain
> brain@jbrain.com  
> www.jbrain.com
I would not worry because of the warning as in this case our purpose was 
to infer a latch. FPGA and CPLD tools warn users for inferring a 
transparent latch because it is a common mistake that a programmer wants 
to create a Combinational Logic but infers a latch due to the missing 
else statement in my case (condition for ~gate_in).
Your workaround is however also ok, I have just one concern.

always @(negedge gate_in)

begin

   if(!gate_in)

     r_w_latched <= r_w_6502;

end


In this part I am not sure whether this will ever meet the if 
requirement. Will gate_in be low already in your condition check? Maybe 
yes as it is combinational logic. Need to test that.
Otherwise the code is ok.

Istvan