Re: 6502 to 7501/8501 converter

From: Gerrit Heitsch <gerrit_at_laosinh.s.bawue.de>
Date: Mon, 18 Jun 2018 16:54:55 +0200
Message-ID: <49d3bb2a-3cdc-9554-6498-edc299596c58@laosinh.s.bawue.de>
On 06/18/2018 10:04 AM, Jim Brain wrote:
> Is there a document that explains the purpose of MUX/GATE_IN?  Why did 
> the 264 series need to latch the R/W line and why did they need to do it 
> in the CPU in such an inefficient way?

The reason, as I understand it, is to make sure that R/W stays LOW long 
enough during a write cycle. Remember, the 264 does switch the CPU to 
double clock if TED doesn't need the bus. AEC is HIGH all the time 
during that period. This means that all signals from the 7501 are 
suddenly active only half as long.

Most RAMs don't seem to care since people have reportedly used 6510 in 
an adapter with R/W connected directly without issues.

Maybe Bil can shed some light on it? Assuming he reads this...

I have captured write cycles on the logic analyzer. R/W depends on MUX 
and can only change state with the rising edge of MUX. Mail me if you 
want the images.

  Gerrit
Received on 2018-06-18 17:00:04

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