Re: 6502 to 7501/8501 converter

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Mon, 18 Jun 2018 21:45:10 +0200 Message-ID: <5e0269a3-1f77-26a2-b8e1-7e9c951ba324@laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 06/18/2018 09:18 PM, Mario Kienspergher wrote:
> OK, next try ... answering to the list ... sorry.
> 
>> I also have images from my scope which show the same behaviour. What's 
>> left now is to explain that behaviour.
>>
>>  Gerrit
> 
> The TED system manual of which scans were presented here some time ago 
> explains the behaviour quite well including timing diagrams. It 
> correspondens to the HDL implementation if I understand it correctly.
> 
> See chapter 5.5.2:
> * R/W from the 6502 core is put through transparently to the R/W pin if 
> MUX is HIGH and is latched when MUX is LOW.
> * If MUX goes back to HIGH the latch is released and the (maybe 
> meanwhile changed) R/W-signal from the core is put through again. This 
> is why you think you see a change at the rising edge. IMHO it is not 
> edge triggered but a transparent latch.

That might be the case, in any way the signal on the scope shows that 
R/W only changes state with rising edge of MUX. I didn't guess what's 
behind that behaviour.

Any circuit that wants to emulate the 7501 will have to behave the same, 
if that takes a latch, fine by me.

  Gerrit