Re: DMA successes with Verilog

On 6/19/2018 6:56 PM, Mia Magnusson wrote:
> Den Tue, 19 Jun 2018 09:35:02 +0100 skrev smf <smf@null.net>:
>> On 16/06/2018 20:34, Spiro Trikaliotis wrote:
>>
>>> What about JSR (two consecutive pushes), or an IRQ, NMI or BRK
>>> (three consecutive pushes)?
>> Isn't that safe because the first write to the stack is followed by a
>> further write to the stack?
I read Spiro's point as if you halt immediately after the first write, 
the CPU doesn't ack your !RDY request for a few more cycles but will 
happy try to store the data in the stack and such, which won't go 
anywhere, because you pulled AEC low and thus the address and data lines 
went HiZ.

Which, I assume will cause the CPU to potentially go into space, as it 
will then jump to some code from which it cannot return.

I suppose all will work OK if you essentially treat the CPU as off the 
rails after each initial DMA:

  * DMA some data to the RAM
  * release DMA, but hit Ultimax Mode so you can feed data to the CPU.
    (doesn't handle first 4kB, so need to fix that issue)
  * Feed it some specific opcodes and data to put the CPU back into a
    known state.
  * release Ultimax mode



-- 
Jim Brain
brain@jbrain.com
www.jbrain.com