Re: DMA successes with Verilog

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Wed, 20 Jun 2018 17:03:58 +0200 Message-ID: <e3307f86-d6c7-d113-7767-42d753daeef5@laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 06/20/2018 02:16 AM, Jim Brain wrote:
> On 6/19/2018 6:56 PM, Mia Magnusson wrote:
>> Den Tue, 19 Jun 2018 09:35:02 +0100 skrev smf<smf@null.net>:
>>> On 16/06/2018 20:34, Spiro Trikaliotis wrote:
>>>
>>>> What about JSR (two consecutive pushes), or an IRQ, NMI or BRK
>>>> (three consecutive pushes)?
>>> Isn't that safe because the first write to the stack is followed by a
>>> further write to the stack?
> I read Spiro's point as if you halt immediately after the first write, 
> the CPU doesn't ack your !RDY request for a few more cycles but will 
> happy try to store the data in the stack and such, which won't go 
> anywhere, because you pulled AEC low and thus the address and data lines 
> went HiZ.

The 65xx will not ACK the !RDY in any way, so you have to do what VIC is 
doing, deassert RDY 3 cycles before you need the bus. Only then can you 
be sure that you can take over.

And, if used in a C64, you also need to take VIC's badlines into account.

  Gerrit