Re: DMA successes with Verilog

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Thu, 21 Jun 2018 17:35:28 +0200 Message-ID: <26fd9ade-607e-9b1f-9762-1f6f38fc82f2@laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 06/21/2018 10:19 AM, Michał Pleban wrote:
> Gerrit Heitsch wrote:
> 
>> After looking at the schematics, I think the only surefire way would be
>> to wait for the end of a badline or sprite access and then take over the
>> bus. That way VIC has done the heavy lifting for you, the CPU has been
>> halted properly.
> 
> But when the display is turned off, that is not gonna happen, right?

Correct... So you only have 2 choices... Either make sure the display is 
turned on when you take over the bus or you can't guarantee the system 
is in a stable state. And if the display is turned on, you have to 
monitor the BA signal to see when VIC wants the bus.

  Gerrit