Re: DMA successes with Verilog

Den Thu, 21 Jun 2018 17:35:28 +0200 skrev Gerrit Heitsch
<gerrit@laosinh.s.bawue.de>:
> On 06/21/2018 10:19 AM, Michał Pleban wrote:
> > Gerrit Heitsch wrote:
> > 
> >> After looking at the schematics, I think the only surefire way
> >> would be to wait for the end of a badline or sprite access and
> >> then take over the bus. That way VIC has done the heavy lifting
> >> for you, the CPU has been halted properly.
> > 
> > But when the display is turned off, that is not gonna happen, right?
> 
> Correct... So you only have 2 choices... Either make sure the display
> is turned on when you take over the bus or you can't guarantee the
> system is in a stable state. And if the display is turned on, you
> have to monitor the BA signal to see when VIC wants the bus.

No, you also have the option of following the CPU activity and thus be
sure that you don't start the DMA in a state where there is a risk of
unwanted extra accesses to the I/O addresses. Worst case that would
need half of a 6502 core in programmable logic but it must be possible
to simplify this a lot.

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