On 7/7/2018 3:56 PM, Michał Pleban wrote: > Jim Brain wrote: > >> Yes, and no. It is easier to set up the 8 port PC-based LA, so I added >> code in the CPLD to activate a pin when the address was reached, and >> then traced it and the port values and a signal indicating whether the >> port was showing the $0 or $1 value. I see that sometimes, the port >> changes to #$1 a number of times, and then it shows your address. The >> number of tests varies. > There SHOULD be $01 appearing, because KERNAL starts testing the RAM in > the first bank. We should analyze closely the last time that it appears, > because it is the offending instruction. Yep, and I see it, but it might be that the CPU does not. > > I have an Intronix 34 logic analyzer which can make traces with very > high resolution. If you sent me the two boards, I could make detailed > traces of what's happening. Not sure the old board has any value. I am awaiting a WDC 65C02S to test. If that does not shed light, I'll solder up a second one of the new unit, test it here and send one. Do you have a Xilinx XPLD/FPGA programmer? Jim > > Regards, > Michau. > -- Jim Brain brain@jbrain.com www.jbrain.comReceived on 2018-07-08 09:00:04
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