On 13/07/2019 21:47, Gerrit Heitsch wrote: > But that's not possible, either an adress bit is 1 or it is 0, so any > address will select exactly one cell. > That is the mirage you want to project when designing a computer, but it's really all just dirty analogue. On 14/07/2019 11:03, Gerrit Heitsch wrote: > Correct... But we also have a latch between the SRAM and VIC, at least > for A0 - A7 which gets locked by /RAS going LOW. The /CS for the SRAM > goes low once /CAS and /RAS are both LOW. From what I understand about > the VSP bug is that the address lines change very close to /RAS going > LOW. Since the SRAM is not active at that time (/CS still HIGH), it > doesn't care what the address lines do as long as they are stable for > long enough before /CAS goes LOW. I thought VSP bug changed the address bits while RAS was low. Which you'll have to forgive me if I'm wrong, but I thought a latch normally followed the inputs until the strobe was released & the standard VSP fix is essentially an intelligent latch. I'm sure someone tried an SRAM conversion and posted here that they still had issues with VSP. If it works now then either it's using different sram or a different circuit. I don't see the point in doing an sram conversion, unless the dram is dead (which is possibly true).Received on 2020-05-29 22:21:40
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