Re: 250466 PCB curiousness

On 7/14/19 1:43 AM, Segher Boessenkool wrote:
> On Sat, Jul 13, 2019 at 10:47:08PM +0200, Gerrit Heitsch wrote:
>> On 7/13/19 9:35 PM, Segher Boessenkool wrote:
>>> On Sat, Jul 13, 2019 at 06:56:24PM +0200, Gerrit Heitsch wrote:
>>>> On 7/12/19 10:28 PM, smf wrote:
>>>>> On 11/07/2019 16:14, Gerrit Heitsch wrote:
>>>>>> SRAM doesn't care what you do with the address lines during a read,
>>>>>
>>>>> It doesn't? AFAIK the memory is still organised in rows and columns, a
>>>>> read still opens a line and connects it to something that reads the line.
>>>>
>>>> Yes, but reading doesn't change the state of a cell, you just read the
>>>> state of the flipflop representing the cell. So, if VIC changes the
>>>> adress lines mid cycle (which is what happens with the VSP bug), the
>>>> SRAM doesn't care. It will supply VIC with the data the address lines
>>>> select. If those change then different data will be supplied. VIC might
>>>> read garbage, but the contents of the SRAM won't change.
>>>
>>> If two addresses are (for a moment) selected at the same time, it depends
>>> on the SRAM implementation.
>>
>> But that's not possible, either an adress bit is 1 or it is 0, so any
>> address will select exactly one cell.
> 
> The lines do not switch in 0 time.

Correct... But we also have a latch between the SRAM and VIC, at least 
for A0 - A7 which gets locked by /RAS going LOW. The /CS for the SRAM 
goes low once /CAS and /RAS are both LOW. From what I understand about 
the VSP bug is that the address lines change very close to /RAS going 
LOW. Since the SRAM is not active at that time (/CS still HIGH), it 
doesn't care what the address lines do as long as they are stable for 
long enough before /CAS goes LOW.

  Gerrit