VIC-II cache corruption

Hi. I was trying to figure out screen corruption during VSP (or DMA Delay, or 
whatever it's called.)

Apparently the VIC-II video chip has a 40x12 bit cache (I guess it is a sort of 
built-in SRAM) to store the current row of 8-bit characters along with 4 bits 
for color information.

There are 40 word lines connected to the cache, let's call them W0 through W39. 
There is a mechanism in the chip that turns on each word line during one half of 
the clock cycle in sequence. The sequence cannot be interrupted, i.e. once you 
turn on W0, all remaining 39 word lines will be activated during the next 39 
clock cycles.

If you trigger a bad line at the right moment you can activate two word lines at 
once. This occurs not at the bad line itself, but at the start of the next line, 
when the first word line is activated. This will then interfere with the 'chain' 
of word lines that was still running from the manual bad line trigger.

A bit of ascii art to illustrate:

[manual trigger of bad line]
  W0
   W1
    W2
     W3
      W4
[... W5 - W36 skipped - start of next line ]
  W0                               W37
   W1                               W38
    W2                               W39
     W3
      W4
       etc.

Now the effect of this appears to be that the cache then gets corrupted, and 
characters (and colors) will appear duplicated. But even weirder still, a 
character can also influence the character next to it. Now this I just do not 
understand. One could argue that since this is undefined behaviour, anything 
could happen.

Some videos that illustrate what I am talking about:

https://youtu.be/Cn7QAWqhBjk
https://youtu.be/is1tfnGRh90

Code that you can run to try for yourself is at
http://www.michiel.boland.org/50demo3.s.txt

I was wondering if any more research has been done into this.

Cheers
Michiel