Re: VIC-II cache corruption

On Sat, Oct 19, 2019 at 06:01:56PM +0200, Michiel Boland wrote:
> Apparently the VIC-II video chip has a 40x12 bit cache (I guess it is a 
> sort of built-in SRAM) to store the current row of 8-bit characters along 
> with 4 bits for color information.

Yes, it's a simple SRAM, 40 words, 12 bit each.

> There are 40 word lines connected to the cache, let's call them W0 through 
> W39. There is a mechanism in the chip that turns on each word line during 
> one half of the clock cycle in sequence.

The whole cycle, in fact.  It's a simple chain of inverters, with pass
gates for the phi1 and phi2 half clocks interleaved.  The bitlines are
only read or written for part of the cycle.

During the "bad" lines, the VIC-II fetches the character data, and it is
written to the currently selected 12-bit word.  During all lines where the
matrix is active, whatever is on the bitlines (there are two per bit) is
sensed and output.

Each cell is just two coupled inverters.

> The sequence cannot be 
> interrupted, i.e. once you turn on W0, all remaining 39 word lines will be 
> activated during the next 39 clock cycles.
> 
> If you trigger a bad line at the right moment you can activate two word 
> lines at once.

Hrm.  I should look at how this works.

> This occurs not at the bad line itself, but at the start of 
> the next line, when the first word line is activated. This will then 
> interfere with the 'chain' of word lines that was still running from the 
> manual bad line trigger.

So the "manual trigger" starts the chain somewhere halfway (horizontally)
on the screen?  Huh.

> Now the effect of this appears to be that the cache then gets corrupted, 
> and characters (and colors) will appear duplicated. But even weirder still, 
> a character can also influence the character next to it. Now this I just do 
> not understand. One could argue that since this is undefined behaviour, 
> anything could happen.
> 
> Some videos that illustrate what I am talking about:
> 
> https://youtu.be/Cn7QAWqhBjk
> https://youtu.be/is1tfnGRh90

Much fun :-)

> Code that you can run to try for yourself is at
> http://www.michiel.boland.org/50demo3.s.txt
> 
> I was wondering if any more research has been done into this.

So, the first "activated" cell puts 1 and 0 on the bitlines, while the
other activated cell does 0 and 1.  This being NMOS, transitioning to 0
is faster than transitioning to 1, so the bitline with the bigger load
(that is the "positive" one iirc) will become 0 and the other 1 (remember,
the cells are cross-coupled inverters).  So the effect is quite stable
and predictable.

Your exact thing I don't quite see, but I'll ponder it :-)


Segher