Re: Accessing the C64 memory between 65xx chips operations.

From: groepaz_at_gmx.net
Date: Sun, 19 Apr 2020 16:15:51 +0200
Message-ID: <5161131.rdbgypaU67_at_rakete>
Am Sonntag, 19. April 2020, 15:52:25 CEST schrieb tokafondo:
> <http://cbm-hackers.2304266.n4.nabble.com/file/t374905/Captura_de_pantalla_d
> e_2020-04-19_14-42-34.png>
>
> This is a timing I've though of the memory accesses the 65xx chips does
> during a 1Mhz cycle.
>
> After posting in other places, it seems that the actual /free/ time the
> memory is *not* accessed is not /always/ the same.
>
> So I'm thinking that after pinning in a logic analyzer with high resolution
> and large logging capabilities, /holes/ in the timing could be found so an
> external /third player/ could be fit to make it access the memory with no
> intervention of the VIC or the CPU -- talking about the C64 here.
>
> That would open the posibility of a /dual core/ C64, where an external CPU
> could do things /a/side or /be/sides the main one, like drawing graphics
> while the 6510 is doing other things, or making fast calculations.
>
> Having the dot clock output pin in the expansion port would do things
> easier, as everything would be clocked at the same speed the VIC is ticking.
>
> Comments, corrections and discussions are not only welcome but encouraged.

it could work - however, keep in mind the access scheme is not fixed, the
VICII will use more bandwidth in badlines, and when sprites are active (have a
look at the "VIC Article" by christian bauer)


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Received on 2020-05-30 01:26:46

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