On 4/19/20 3:52 PM, tokafondo wrote: > <http://cbm-hackers.2304266.n4.nabble.com/file/t374905/Captura_de_pantalla_de_2020-04-19_14-42-34.png> > > This is a timing I've though of the memory accesses the 65xx chips does > during a 1Mhz cycle. > > After posting in other places, it seems that the actual /free/ time the > memory is *not* accessed is not /always/ the same. > > So I'm thinking that after pinning in a logic analyzer with high resolution > and large logging capabilities, /holes/ in the timing could be found so an > external /third player/ could be fit to make it access the memory with no > intervention of the VIC or the CPU -- talking about the C64 here. You're still limited to the timing imposed by PHI0 and, for RAM access, by the timing of /RAS and /CAS (both generated by VIC and /CAS routed through the PLA). So you could only use the bus during the time VIC doesn't need it. Since VIC does dummy accesses, you'd have to disconnect it's address lines from the RAM and provide your own multiplexing since the 74LS257 used by the CPU are offline during VIC's part of the cycle. > Having the dot clock output pin in the expansion port would do things > easier, as everything would be clocked at the same speed the VIC is ticking. dot clock is available at the expansion port, but all timing is related to PHI0 though. All in all it might be possible, but not without some serious hardware redesign. GerritReceived on 2020-05-30 01:27:02
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