Thanks both for your answers. As I tried to show in the timing diagram, I'm not talking about kick /in/ during the high or low phase of the clock, /instead of/ the VIC or the 6510, but /between/ their turns. The duration of the memory access of the VIC, no matter how much it does, (64, 65, 40 more, etc.) its more or less /fixed/. It lasts about 250 ns, as others have said to me. But if my calculations are right, one cycle of the CPU, running at ~1mhz (a bit more in NTSC, a bit less in PAL) lasts 1000ns. And if there is a low phase and a high phase in every cycle, then every half cycle (low phase for VIC, high phase for CPU) lasts ~500 ns. Then... in every half cycle that lasts ~500 ns, we have the right chip sending the access type (read or write), accessing the bus, addressing the memory location, moving the data (reading or writing), and then releasing the bus, until the next half cycle. The next half cycle, it could be the VIC again to fetch more data, to refresh the DRAM, or whatever, OR the CPU to do its own things. Between that 'release the bus' and the next 'accessing the bus' there are **IN THEORY** a few 100's of ns where the bus is not used and *THAT* is where I think a third /player/ could kick in to make an additional read or write. -- Sent from: http://cbm-hackers.2304266.n4.nabble.com/Received on 2020-05-30 01:27:19
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