Re: 7501/8501 R/W gate in

I'm not sure if this is the latest version of the code (I haven't set up 
a repository as I was not interested
in the project anymore) but here's the code we've used on Jim Brains 
"Fake7501" Hardware (just google for it).

I cannot recall if we had to fix the hardware too... but in case: 
Shouldn't be too difficult - except for all the
freeriders out there.


`timescale 1ns / 1ps

module Fake7501(
     input           clock_i,
     input           _reset_i,
     input           aec_i,
     input           gate_in_i,
     input           r_w_6502_i,
     input   [15:0]  address_6502_i,
     input           rdy_i,
     input           _irq_i,

     output          r_w_7501_o,
     output  [15:0]  address_7501_o,

     inout   [7:0]   data_6502_io,
     inout   [7:0]   data_7501_io,
     inout   [6:0]   pio_io);


     //
     // Handle inouts
     //
     wire [7:0] data_6502_i = data_6502_io;
     wire [7:0] data_7501_i = data_7501_io;
     wire [6:0] pio_i = pio_io;


     //
     // GATE IN logic
     //
     reg r_w_latched;
     reg aec_latched;

     always _at_(gate_in_i, r_w_6502_i, aec_i)
     begin
         if (gate_in_i)
         begin
             r_w_latched = r_w_6502_i;
             aec_latched = aec_i;
         end
     end


     //
     // Handle I/O port registers
     //
     reg [6:0] data_pio;
     reg [6:0] ddr_pio;

     wire ce_pio = (address_6502_i[15:1] == 15'h00);
     wire ce_0000 = ce_pio & !address_6502_i[0];
     wire ce_0001 = ce_pio & address_6502_i[0];

     always _at_(negedge clock_i, negedge _reset_i)
     begin
         if (!_reset_i)
         begin
             ddr_pio <= 7'h00;
             data_pio <= 7'h00;
         end
         else begin
             if (!r_w_6502_i & ce_0000)
             begin
                 ddr_pio <= {data_6502_io[7:6], data_6502_io[4:0] };
             end
             else if (!r_w_6502_i & ce_0001)
             begin
                 data_pio <= {data_6502_io[7:6], data_6502_io[4:0] };
             end
         end
     end


     //
     // Handle outputs
     //

     // Data bus to outside world is tristated during PHI1, PIO accesses 
and AEC being low
     wire data_7501_tristate =
         ~clock_i |
         ce_pio |
         ~aec_latched;

     assign r_w_7501_o = aec_latched ? r_w_latched : 1'bZ;
     assign address_7501_o = aec_i ? address_6502_i : 16'hZZ;

     // Deactivate data bus to 8501 if 6502 wants to read or it's tristated
     assign data_7501_io = (r_w_6502_i | data_7501_tristate) ? 8'hZZ : 
data_6502_i;

     // Put either PIO_DDR, PIO_DATA or the read databus on the bus to 6502
     wire [7:0] data_to_6502 =
         ~ce_pio ? data_7501_i : (address_6502_i[0] ? {pio_i[6:5], 1'b0, 
pio_i[4:0]} : {ddr_pio[6:5], 1'b0, ddr_pio[4:0]});

     // Disable output from CPLD to 6502 if 6502 wants to write
     assign data_6502_io = ~r_w_6502_i ? 8'hZZ : data_to_6502;

     assign pio_io[6] = ddr_pio[6] ? data_pio[6] : 1'bZ;
     assign pio_io[5] = ddr_pio[5] ? data_pio[5] : 1'bZ;
     assign pio_io[4] = ddr_pio[4] ? data_pio[4] : 1'bZ;
     assign pio_io[3] = ddr_pio[3] ? data_pio[3] : 1'bZ;
     assign pio_io[2] = ddr_pio[2] ? data_pio[2] : 1'bZ;
     assign pio_io[1] = ddr_pio[1] ? data_pio[1] : 1'bZ;
     assign pio_io[0] = ddr_pio[0] ? data_pio[0] : 1'bZ;

endmodule


On 30.08.2020 20:57, Francesco Messineo wrote:
> On Sun, Aug 30, 2020 at 8:49 PM Frank Wolf <webmaster_at_frank-wolf.org> wrote:
>> GATE_IN just latches R/W# and AEC... that's all. Nothing more.
>>
> this changes *a whole lot* (at least in my reproduction...).
> Gated AEC to R/W latch means that R/W remains driven after AEC going
> low until GATE_IN goes high again...
> Which is a bit of a nightmare since I'm out of free cells...
> Does anyone know why this particular thing is needed (delay the R/W
> hi-z until next gate_in)?
>
> Thanks
> Frank
>
>