From Kiwi - a 68k Homebrew computer <https://www.ist-schlau.de/hardware.html> ... * > 8 to 16 bit buffer interface * > While the CPU, memory and most of the subsystems are connected with 8 bit > width, there are two subsystems which use a 16 bit bus. These are the > ATA/IDE interface and the Ethernet interface (CS8900a). To access 16 bit > with an 8 bit CPU, one has to break accesses. One 16 bit access works out > as two consecutive 8 bit accesses. This works as follows. <http://cbm-hackers.2304266.n4.nabble.com/file/t374905/8-16bit-buffer.png> > > To read an 16 bit word, the device is accessed with the first access. > While it provides its data, the lower half (D0-D7) is read by the CPU > while the upper half (D8-D15) is latched (U44). The second access just > enables the output buffer of this latch. > To write an 16 bit word, the device is accessed with the second access. > The data provided in the first access is latched (U45). With the next > access, the latched data is provided as low byte (D0-D7), while the CPU > data is provided as high byte (D8-D15). > As the MC68008 always accesses low byte first, word addressing modes with > 16 bit are possible. In this way, the address line A0 can be used to > determine the current state of an access. A0 is low for the first and high > for the second access. Can this be applied to the 6502/816, software and hardware wise? -- Sent from: http://cbm-hackers.2304266.n4.nabble.com/Received on 2020-12-13 16:53:37
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