On Thu, Jan 07, 2021 at 07:12:33AM +0100, Gerrit Heitsch wrote: > On 1/7/21 4:12 AM, Segher Boessenkool wrote: > >>You shouldn't do that though. > > > >We only did it to show what causes the problem, yup. > > > >But would it even cause any problems? You're only delaying #CS by 40ns > >or so (if you do it right ;-) ), that's well within allowed timing, it > >just avoids the annoying light-grey blips. > > Yes, but you would also delay /CS for some ns over it going HIGH again. > Some other chip might want the databus at the same time. The VIC also uses the R/#W signal for tristating the data bus drivers (that and #CS, nothing else). So this should be good still. Nevertheless I agree that this is just asking for trouble :-) SegherReceived on 2021-01-07 20:00:22
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