Re: CIA old/new?

Hi!

On Fri, Jan 08, 2021 at 12:50:39PM +0100, silverdr_at_wfmh.org.pl wrote:
> > On 2021-01-07, at 19:30, Segher Boessenkool <segher_at_kernel.crashing.org> wrote:
> >> As I mentioned already in this thread - only (some) of the HMOS-II chips expose the problem.
> > 
> > And yet, everything that matters on those chips is identical, and timing
> > difference on the chip (different process) cannot be anywhere near 40ns
> > (half a dot clock is 60ns!)
> 
> I am not sure I understand you. IF everything that matters was identical, we wouldn't see the difference, would we?

I am simply saying that all of the circuitry that matters on those chips
is 100% identical (some other things were changed, but nothing that
affects any of this).

Timing differs per copy of the chip even, or batch, or whatever -- but I
am saying it is very unlikely that can show a 30ns (about half a pixel,
which is what the artifact is) difference, while the board difference
is 35ns.

> If we exclude on-chip propagation times then there has to be something else that "matters" because with the same external timing, still only (some) HMOS-II chips expose the problem.

I have seen no proof of that claim, btw -- of course it is hard to show
supporting evidence for a negative claim, it will need a lot of
independent observations.

> >> Among those which do, it may depend on the chip's temperature (problem fades with temperature rising). OTOH no single NMOS based VIC expose the issue even with the same board timing. Yes, you can patch the _CS line with a cap and crudely work the problem around this way
> > 
> > Which I said is not a good solution, only a simple way to show the
> > origin of the problem.
> 
> Again I am unsure I understand. How do you define "origin" of the problem? Did you conclude that the board's timing is the "origin"?If yes, then after testing lots of combinations my opinion is that the "origin" of the problem lies in the chip. And I give my reasoning.

Ha no.

The origin of the problem is that when the pixel colour is taken from a
colour register, it isn't latched at all.  If you write the register at
the same time, you see whatever is on the (VIC-internal) data bus.  And
that bus is precharged, so the first pixel will be light-grey for about
its first half on affected systems (and will be the old colour on others).

I am saying this timing difference cannot be explained by just the
different chip process.  It *can* be true that it will never show with
older chips, but I doubt it, see my reasoning above.

> >> but I say it once again: with the very same _CS timing no NMOS VIC produces the annoying sparkles. So it is up to whoever reads this to decide whether this is a bug of the board/PLA/replacement or the actual HMOS-II VIC. For me it's the latter.
> > 
> > My position is it is not a bug at all, it is as designed.  And it
> > wouldn't even be noticed until very many years later :-)
> 
> That "many years later" boil down to actually a few weeks after the narrow boards started to ship in quantities - people quickly started to ask to "fix" their computers. Mostly due to the "faulty" SID, which "couldn't play samples" but also due to the sparkles on the screen. Back then the only thing I could tell them was "if that annoys you - get an older model". I didn't know I could put a cap to make them happy ;-)

I only heard about the sparkle thing, well, I don't know how long ago,
but somewhere in the 2000's.  Apparently I just missed it :-)


Segher