Re: Independent CPU/VIC-II setup

From: Michał Pleban <*lists_at_michau.name*> Date: Sat, 29 May 2021 22:46:39 +0200 Message-ID: <60B2A82F.6010808_at_michau.name> · lists_at_michau.name

Jim Brain wrote:

> This will work, if you create 2 address/data busses.  Put some '541s and
> '245s on the VIC-II bus to only connect it to the main Address/Data bus
> when the CPU is accessing the VIC-II memory space.  Then, your number
> above will get much closer to 8MHz.

Isn't something like this used in the P500 (where VIC-II can access RAM
in bank 0, and the CPU can access all banks)? It might be useful to
analyze the P500 schematics to get a grasp on how they separated the
busses there (although the 6509 still gets its clock from the VIC in
that setup).

Regards,
Michau.