I'm pretty sure they aren't seperate enough for the vic2 and cpu to have access to different areas of ram at exactly the same time. That kind of setup is pretty complicated and the p500 is already complicated enough. With faster ram you could immediately perform the read and latch the result for the vic2, so it wouldn't be at the same time but it would hold the bus for less. It is still a little complicated as you will need the latch to disappear when doing a cpu to vic2 read/write. On 29/05/2021 21:46, Michał Pleban wrote: > Isn't something like this used in the P500 (where VIC-II can access RAM > in bank 0, and the CPU can access all banks)? It might be useful to > analyze the P500 schematics to get a grasp on how they separated the > busses there (although the 6509 still gets its clock from the VIC in > that setup). > > Regards, > Michau. > >Received on 2021-06-01 19:00:05
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