It is not. Source: Logic analyzer traces I've captured. :) On Sat, Nov 6, 2021 at 11:04 PM Claudio Sánchez <tokafondo_at_gmail.com> wrote: > > > On 11/6/21 6:55 PM, Claudio Sánchez wrote: > >>> If you can find a chip that needs 7.88mhz on pal and 8.18mhz on ntsc > >>> then sure, but you're then just using the DOT clock as a cheap way of > >>> getting a clock. > >> > >> Well... at first it is. It's a cheap way of getting a clock. > >> > >> phi2 pin is AFAIK a copy of what the 6510 gives out to the rest of the system, so when the 6510 gets halted by the VIC-II... is phi2 affected? > > > > No, the 6510 gets halted by the RDY pin, clock is not affected. > > > > Gerrit > > > > > > Yes, so the fact that the VIC-II asks the 6510 to stop doesn't mean that when the latter is halted, its phi2 output also gets halted, or is it? >Received on 2021-11-07 07:00:02
Archive generated by hypermail 2.3.0.