Re: 1571/1581 Sources: Macro WDTEST inserting NOP before reading WD177x status register / writing command register

Hi,

On Fri, Mar 11, 2022 at 6:13 PM Spiro Trikaliotis
<ml-cbmhackers_at_trikaliotis.net> wrote:
>
> Hello,
>
> I am trying to understand the sources of the 1571 and 1581 drives.
>
> In the original drive sources of the 1571 and 1581 (as found on
> zimmers.net), there is a macro WDTEST:
>
> WDTEST  .macro
>         .ife <*!.$03
>         nop
>         .endif
>         .endm
>
> I am not completely familiar with the syntax of the assembler used, but
> if I understand it correctly, it issues a NOP if bit 0 and bit 1 of the
> PC are both 0 - that is, the PC address is divisble by 4.

wild guess:
The WD1770 in the Commodore 1571 (and I guess in the 1581 too, but
I've never seen one) has its chip select line
qualified with the wrong clock. Let me explain better: when a
peripheral device must be connected to the 6502's bus, it either has a
phi2 input
or we usually qualify the select to happen during phi2 high.
Sometimes, for example with static rams, it's usually enough to
qualify the write signal to phi2 high only.
Now, the 1571 was made when all the good engineers had already left
Commodore by a long time and to save one gate, they used phi1 LOW
OR'ed with the decoded
address range to obtain the WD1770 select.
Phi1 and phi2 aren't an inverted replica of each other. The low phase
of phi1 is LARGER than the high phase of phi2 and phi2's low phase is
larger than phi1 high phase,
that's to avoid any possible bus contention if devices use phi1 and
phi2 HIGH phases to access the same bus (like on the old dual cpu
drives for example).
Now, if one uses phi1 as "poor man's" inverted phi2, it turns out that
the chip select to the WD1770 might happen too early (phi2 not yet
high) and cause unpredictable
behaviour.
Since also the WD1770 need two address lines and they are supplied by
A0 and A1, it was probably wise to never have both A0 and A1 both low
just before a real access
to this device, since its chip select has the wrong timing and maybe
A0=A1=0 was the worst possible fake access to this device.
However, they should have corrected the hardware, not make this
software workaround.
VIA/PIA and all other native 6502 peripherals have a phi2 input, so
the address decode glue logic need not worry about qualifying the
selects against phi2 high phase.
HTH
Frank IZ8DWF