Re: 1571/1581 Sources: Macro WDTEST inserting NOP before reading WD177x status register / writing command register

Hello Gerrit,

* On Fri, Mar 25, 2022 at 06:56:49AM +0100 Gerrit Heitsch wrote:
> On 3/24/22 22:33, Spiro Trikaliotis wrote:
> > Hello Gerrit,
> > 
> > * On Thu, Mar 24, 2022 at 10:04:11PM +0100 Gerrit Heitsch wrote:
> > > On 3/24/22 21:45, Spiro Trikaliotis wrote:
> > 
> > > The NOP only makes sense if there is something happening inside the 177x
> > > that needs a bit of extra time to finish before the next access to whatever
> > > register can happen.
> > 
> > There is, as I wrote in my first posting.
> > 
> > The 6502 absolute addressing is as follows (looking into the MOS 6502
> > programming manual, appendix E.3):
> > 
> > Clock    Adress Bus      PC      DAta bus    comments
> > Cycle
> >    1        PC           PC + 1    OP CODE    fetch op code
> >    2        PC + 1       PC + 2    ADL        fetch ADL
> >    3        PC + 2       PC + 3    ADH        fetch ADH
> >    4        ADH,ADL      PC + 3    Data       fetch Data
> >    5        PC + 3       PC + 4    OP CODE    fetch new op code, execute old op cod
> > 
> > So, if I start an access to the WD177x status register at an PC with
> > A0=A1=0, then A0=A1=1 will end in clock cycle 5. The CPU will try to
> > force these values of A0 and A1.
> 
> Yes, but by that time the /CS-signal for the WDC will have been HIGH for
> quite some time so it won't feel bothered by what's on A0 und A1.

Are you sure?

Looking at the data sheet and taking into account the timings for 2 MHz:

PHI1 goes HIGH at T_01+ after PHI0 going low; this is 10 ns (min.) to 70 ns (max.)

PHI2 goes LOW at T_02- after PHI0 goes low; this is 5 ns (min.) to 65 ns (max.)

So, in the best case, PHI1 and PHI2 have a difference of 0 ns. In the
worst case, we have a difference of 65 ns.

T_ADH, the time that the 6502 holds the address bus after PHI2 goes LOW, is 30 ns (min.).

T_ADS, the time after that the 6502 has the new address bus values after
PHI2 goes low is 140 ns (max.)

In the time between the 30 ns hold time and the 140 ns setup time, the
values of the address bus lines are not defined! Indeed, even the timing
diagram show the address and data bus shaded. Don't let the diagram fool
you, it looks as if PHI1 changes to high in the time before this
happens. Unfortunately, the timing values show that this cannot be
guaranteed.

So, in the time where the lines are not defined, there might be some
analogue effect, or the 6502 might update low byte and high byte in any
order - who knows? (Perhaps the guys at visual6502?)

And the PHI1 going HIGH (up to 65 ns after PHI2 low) can fall exactly in
this time span of 30 ns .. 140 ns after PHI2 goes low, in which the
address bus is undefined by the spec.
 
> No, you didn't access the WD177x since the upper address lines don't show
> the pattern where the WD is located and that will have forced /CS for the WD
> HIGH before PHI1 becomes LOW again.

As I showed above, you're ignoring the time at which the outputs of the
address lines (and the data bus lines, btw) are not defined in the data
sheet.

Regards,
Spiro

-- 
Spiro R. Trikaliotis
https://spiro.trikaliotis.net/