Michal Pleban writes: > silverdr_at_srebrnysen.com wrote on 04.05.2022 15:55: > >> Modern FPGAs with built-in flash and Co. are narrowing the initialisation >> time gap on CPLDs significantly. Unless yours is known to be really slow on >> this, in the C64 context you may be able have a safe margin before the power- >> up cycle releases /RESET line[*]. I take this is important only on power-up >> as during warm RESET your FPGA is already loaded anyway. > > I am not sure at the moment if it's going to be a FPGA at all. I may end up > using a Propeller which is easier to program and cheaper, but unfortunately > it has around 1.5s startup time. > How about extending /RESET until your device is ready ? /UffeReceived on 2022-05-04 18:00:02
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