Re: 6510 RDY and RESET

From: Segher Boessenkool <*segher_at_kernel.crashing.org*> Date: Wed, 4 May 2022 09:36:58 -0500 Message-ID: <20220504143658.GZ25951_at_gate.crashing.org> · segher_at_kernel.crashing.org

Hi!

On Wed, May 04, 2022 at 03:28:31PM +0200, Michal Pleban wrote:
> What would happen if the 6510 got a /RESET signal while the RDY signal 
> is low? At which bus cycle would it stop - before or after reading the 
> reset vector from $FFFC?

VEC0 = T5_00000000 and RDY

if phi2:
  n1126 = VEC0
if phi1:
  VEC1 = n1126 or (VEC1 and not RDY)

VEC0 and VEC1 are the signals for the two vector fetches.  As you can
see, VEC0 is gated by RDY.  The vector isn't fetched while RDY is still
low.

Segher