Re: 6510 RDY and RESET

From: ruud_at_Baltissen.org Date: Wed, 04 May 2022 18:30:30 +0200 Message-ID: <6272AA26.22741.5EA86539_at_ruud.Baltissen.org>

Hallo Michał,

> What would happen if the 6510 got a /RESET signal while the
> RDY signal is low? At which bus cycle would it stop - before
> or after reading the reset vector from $FFFC?

The 6510 stops immediately. That is the behavior if I attach my 
debugger to a C64. I have to single step seven times (IIRC) before I 
get the reset vector.

> Question context: Suppose we have a C64 cartridge built on an
> FPGA. The FPGA needs some time....

Regarding my experince: that should work fine. That the DMA input 
also tri-states the 6510 should be no problem.
--

Kind regards / Met vriendelijke groet, Ruud Baltissen
www.Baltissen.org