6510 RDY and RESET

From: Michal Pleban <*lists_at_michau.name*> Date: Wed, 4 May 2022 15:28:31 +0200 Message-ID: <3e042278-9339-d242-b5d1-1ba6d4b2a883_at_michau.name> · lists_at_michau.name

Hello!

What would happen if the 6510 got a /RESET signal while the RDY signal 
is low? At which bus cycle would it stop - before or after reading the 
reset vector from $FFFC?

Question context: Suppose we have a C64 cartridge built on an FPGA. The 
FPGA needs some time to initialize. Before it does that, it could pull 
down the RDY signal so that the CPU doesn't start before the FPGA is ready.

Regards,
Michau.

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