On Sun, 4 Sept 2022 at 20:31, <silverdr_at_srebrnysen.com> wrote: > > > > On 2022-09-04, at 18:43, Ed Spittles <ed.spittles_at_gmail.com> wrote: > > > > I've just remembered - one of the early successes from the visual6502 > > project was Peter Monta's implementation of the core algorithm on an > > FPGA, running fast enough to work as a 1MHz 6502 in an Atari, using a > > GODIL module. > > Interesting! GODIL modules (AFAIR) were (are?) CPLD based? > > http://www.oho-elektronik.de/index.php?c=1&s=product1 > > These ones? There's one Spartan FPGA based but all are with small > pincount. The larger ones apparently are no longer there. > Indeed, GODILs were FPGA based but unavailable now. (Many FPGA chips are unavailable now.) Do you have more info/reference on that particular implementation? > See the (archived) visual6502 wiki page https://web.archive.org/web/20210405071450/http://visual6502.org/wiki/index.php?title=6502_-_simulating_in_real_time_on_an_FPGA and Peter's repository: https://github.com/pmonta/FPGA-netlist-tools EdReceived on 2022-09-05 19:00:04
Archive generated by hypermail 2.3.0.