> On 2022-09-04, at 18:43, Ed Spittles <ed.spittles_at_gmail.com> wrote: > > I've just remembered - one of the early successes from the visual6502 > project was Peter Monta's implementation of the core algorithm on an > FPGA, running fast enough to work as a 1MHz 6502 in an Atari, using a > GODIL module. Interesting! GODIL modules (AFAIR) were (are?) CPLD based? http://www.oho-elektronik.de/index.php?c=1&s=product1 These ones? There's one Spartan FPGA based but all are with small pincount. The larger ones apparently are no longer there. Do you have more info/reference on that particular implementation? Oh, and I trust there must be a comprehensive compatibility testing "suite" for that somewhere? I vaguely recall something running on a 1541... was it from VICE team?Received on 2022-09-04 22:02:22
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