Re: C128 and 8MHz Z80 (revisited)

On 6/3/2024 5:56 PM, Maciej Witkowiak wrote:
> Hello
>
> With a simple daughterboard, a GAL and a 74LS74 the Z80 in C128 can 
> run at dot clock frequency (almost 8MHz) during its 1MHz phase of the 
> system clock, effectively doubling the speed.
>
> Basic benchmarks written in Turbo Pascal showed me that indeed it is 
> about twice faster.
> CP/M is visibly snappier, to the point of being usable.
>
> There was a message here back in 2002 about a PCB for C128 that 
> boosted Z80 to 8MHz
> https://www.softwolves.com/arkiv/cbm-hackers/7/7361.html
> Unfortunately that device was not fully reverse-engineered and it 
> seems that it was never mentioned again (nor here nor anywhere else). 
> Even linked photo is not available anymore.
>
> Once I saw it, it bothered me like a note that solution exists, 
> scribbled on a margin of a math book.
>
> Here is a schematic of my circuit for that:
>
> https://github.com/ytmytm/c128-z80-8mhz/blob/main/z80-dotclock-gal-and-latch/plots/z80-dot-gal.pdf
>
> There is no PCB design yet because so far I only used a development 
> board, where I missed the fact that /WR or /RESET will be needed.
> Right now I have a daughterboard with GAL+74LS74 plugged into a 
> daughterboard with Z80 plugged into Z80 socket in C128.
>
> Here is the PLD file for GAL programming with the whole logic:
>
> https://github.com/ytmytm/c128-z80-8mhz/blob/main/z80-dotclock-gal-and-latch/gal/z80-dot.PLD
>
> It is written for 22V10 because that's what I had at hand, but 16V8 is 
> enough for that job. For 16V8 just renumber the output pins.
>
> I put the rest of my notes on Github in the project respository, 
> including Kicad files:
>
> https://github.com/ytmytm/c128-z80-8mhz
>
> I didn't try to overclock the original Z80B in my C128, I replaced it 
> some time ago by a Z84C0020 that uses much less energy.
>
> This circuit works fine for me. During tests it was stable for several 
> hours, busy with drawing fractals and calculating pi using Monte-Carlo 
> method. The CPU doesn't even get warm to the touch. Disk I/O worked 
> fine, as well as REU ram disk M: (emulated by UII+).
>
> I also tried using the 16MHz clock signal from VDC (pin 2). The C128 
> would start, but CP/M won't boot. However all my simple tests passed. 
> I suspect that memory access is an issue and some of the memory writes 
> fail.
> But in principle 16MHz clock seems possible.
>
> There are some things I was not able to figure out yet:
>
> 1) How can we keep it simple but run at full speed all the time and 
> stall only on memory and I/O access? It's not clear if the device 
> mentioned in 2002 was really working at 8MHz all the time or just 
> during Z80 turn.
>
> 2) Since I already used ATF22V10 which has asynchronous reset for 
> registers, it should be possible to get rid of 74LS74 with a different 
> assignment of pin 1 (GAL CLK input). I wasn't able to do it. I'm 
> probably doing something wrong - messing up high/low vs 
> active/inactive or my CUPL skills are lacking.
>
> 3) Is it possible to go faster than DOT CLOCK? Even at 16MHz (8 ticks 
> between bus access) it seems that CPU would spend more time being busy 
> rather than waiting for the bus. (No need to bother if point (1) can 
> be done).
>
> ytm
>
I'm not sure the answers to all your questions, but I happen to have 
here a ton of xc9572xl CPLDs in a tiny qfp64 package that nicely fits 
under a 40 pin socket (surplus purchase years ago). With 72 flip flops, 
I am sure the GAL logic and the FF can be placed inside, and some of the 
additional logic I think would be needed to allow the CPU to run at full 
speed on all but memory/IO accesses.  As well, with the CPLD triple 
clock inputs, we could do 1MHz, dot, and 16 or something even faster, 
and tune the logic inside the CPLD to run even faster (I see the ez80 
can be 50MHz clocked, and the unit acts like a 150MHz Z80 at those 
speeds, ignoring RAM slowdowns), and even (if the ez80 is chosen) put a 
bit of on board SRAM on board to bypass needing to slow down for memory 
(just IO, and maybe a window of memory for VIC-II usage, for example).

I'm happy to help on the HW side, and the Verilog side, but I'm not very 
knowledgeable on the Z80 architecture (I want to learn), so lots of 
assistance would be needed there.

And my CUPL is bad as well, but I can give it a try to load the Flop 
into the GAL.

-- 
Jim Brain
brain_at_jbrain.com
www.jbrain.com