Re: C128 and 8MHz Z80 (revisited)

On Tue, Jun 4, 2024 at 4:22 AM Jim Brain <brain_at_jbrain.com> wrote:

> I'm not sure the answers to all your questions, but I happen to have
> here a ton of xc9572xl CPLDs in a tiny qfp64 package that nicely fits
> under a 40 pin socket (surplus purchase years ago). With 72 flip flops,
> I am sure the GAL logic and the FF can be placed inside, and some of the
> additional logic I think would be needed to allow the CPU to run at full
> speed on all but memory/IO accesses.  As well, with the CPLD triple
> clock inputs, we could do 1MHz, dot, and 16 or something even faster,
> and tune the logic inside the CPLD to run even faster (I see the ez80
> can be 50MHz clocked, and the unit acts like a 150MHz Z80 at those
> speeds, ignoring RAM slowdowns), and even (if the ez80 is chosen) put a
> bit of on board SRAM on board to bypass needing to slow down for memory
> (just IO, and maybe a window of memory for VIC-II usage, for example).

I'm happy to help on the HW side, and the Verilog side, but I'm not very
> knowledgeable on the Z80 architecture (I want to learn), so lots of
> assistance would be needed there.
>

Thanks!

I have a dev board with xc9572xl, but haven't got around to install any
programming enviroment yet.
Now that I see that this has a chance to work I will surely give it a try.

I'm no expert on Z80 either so ez80 at this time is out my skill set, but
surely I can start with replicating this circuit - that I already
understand.
With a more capable CPLD and more expressive Verilog it would be easier to
go on with experiments.

And my CUPL is bad as well, but I can give it a try to load the Flop
> into the GAL.
>

I would welcome any ideas. Also if it would be easier for you to express it
in Verliog that would help me learn too.

Here is how it is supposed to work:

0 VIC cycle phase starts, latch is in reset state, latch D input is
constant 1, but due to reset Q output is 0 and negated /Q is 1; Z80 is
stopped as its clock is held low
1) Z80 cycle phase starts, latch goes out of reset, /Q output = WAITLATCH
stays 1, Z80 sees that as inactive /WAIT and runs program, without bus
access requests WAITTRIGGER stays 0
2) Z80 wants to access the bus, WAITTRIGGER will rise to 1; this will cause
latch D input connected to 1 be copied to the output, so /Q becomes 0, Z80
will see that as an active /WAIT and will stop
3) this state will not change until start of the next VIC cycle phase
4) VIC cycle phase starts, latch is reset - will set latch /Q to 1, so for
Z80 /WAIT now becomes inactive; but Z80 won't run because during this
half-cycle the CPU clock signal is not passed at all
5) Z80 cycle phase starts, it can continue because after latch reset /WAIT
is inactive; Z80 accesses the bus so WAITTRIGGER stays 1 until Z80 gets
what it needs from data lines - then it goes back to 0

The idea of this is that during Z80 clock phase when WAITTRIGGER goes from
inactive to active we can latch /WAIT line low to hold it low at least
until the start of VIC cycle.
We release it before/at the start of Z80 cycle it so /WAIT becomes high
again - even though the latch trigger condition is still active.

I guess that is something like asynchronous preset of /WAIT (based on
WAITTRIGGER) with synchronous reset (based on CLK1MHZ) but the preset has
to be edge triggered.

Now that I wrote all of that I think that maybe I fixated too much on /WAIT
signal, I can't avoid flip-flop yet but it seems it could work just as well
by controlling the Z80 clock alone.

ytm