On Thu, Jun 6, 2024 at 5:48 AM Jim Brain <brain_at_jbrain.com> wrote: > If you are using Linux, it should be easy (Xilinx WebPack ISE dload). If > using Windows 10/11, shoot me a personal email, as it's not tough, but it > requires replacing a DLL to get it to work. > Not a problem, I use daily both, but I'm leaning back towards Linux after a long break (even though half of the Linux time is WSL). > WIth the 72 pin CPLD (of which I have a ton, no supply worries there), it > uses 10 or so pins, 1 flip flop, and 4 macro cells. I thought about > pushing more signals into the CPLD, but I thought I'd wait to see what is > interesting, as I barely know the Z80 bus. But, you could easily pull in > all the non Address/Data signals, and with a bit of layout, you can pull > all the address and data lines in (put the speed under SW control, if > desired). I also need to add in a third clock source, which is a PLL that > runs off the dot cock but multiplies the dot clock (with low skew): > > Datasheet: https://www.renesas.com/us/en/document/dst/501-datasheet > > By default, it doubles the input clock, but can do 2x,3x,4x,5x,6x,and 8x, > and also some factions. > > (...) > > I was thinking the same, so I'd recommend adding in a lot of the signals > you'd like to play with, and then you can wire them up in the CPLD and see > what works best. > > Adding in on board RAM is also possible, and using a few register bits to > denote what parts of Z80 RAM you wish to mirror, if any. > > I forked your github project and added my stuff into it my version: > > https://github.com/go4retro/C128-Z80Plus > Thanks a lot for your work and advice! That is more than I could wish for and will keep me busy for a while. I'm super excited to try it out. ytmReceived on 2024-06-07 23:00:01
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