Re: C128 and 8MHz Z80 (revisited)

On Thu, Jun 6, 2024 at 9:28 AM Jim Brain <brain_at_jbrain.com> wrote:

> > My thought: what about using an asynchronous interface? I made one
> towards the expansion bus for the C64 once. Pre-condition: the 6510 is
> halted already, and that is the case here, and check BA.
> > For a read:
> > - wait until the Phi2 is (L)
> > - during Phi2 is (H), latch the data into 573 or equivalent
> > - after Phi2 goes (L), run on full speed again
> I don't think you need the 573.  If a read happens, just wait until phi2
> rises, and then use the Z80 normal CLOCK cycle for 1 cycle to read the
> data (I think it's a 4Mhz clock cycle), and then go back to full speed.
> I don't think you have to wait until Phi2 goes low again, as the Z80 ran
> at 4MHz normally, so the RAM must be able to handle that speed.
>
> During a write:
> > - wait until the Phi2 is (L)
> > - when Phi2 goes (H), output the data on the data bus and start waiting
> > - after Phi2 goes (L), run on full speed again
> Same here, I don't think you need to wait for the entire Phi2 cycle.
> Just enough of it to do the write.


Thank you both for ideas!

Just a note: for reads the data lines for Z80 are already latched in
onboard '373 U12 (clocked by Phi2 and output for Z80 enabled by /RD).
For writes there is U13 - a '244 buffer with output-enable controlled by
U56 (74LS74) + U31 (74LS00) - but I'm not sure what exactly this section
does.

ytm