From: Arndt Övermann (arndt.oevermann_at_freenet.de)
Date: 2004-06-16 21:31:34
Am Dienstag, 15. Juni 2004 08:42 haute ncoplin@orbeng.com folgendes in die
Tasten:
> Hi All,
>
> Well, having finally proven out my DRAM refresh scheme for internally
> mounted 1, 4 or 16MB SIMMs on the weekend, I'm very close to finalising the
> hardware side of this project. A bit of a project overview is given below,
> but the main question I have at the moment is where to map in the control
> registers I need. A logical choice for me is in the VIC I/O space (because
> the device will be a VIC socket plug in), new registers $D03E and $D03F.
> I'm looking at these registers being Write-Only so I can save some decode
> logic. The original Transactor design used the $01 port, but I need more
> bits than are available and this location does have some compatibility
> issues (GEOS's calculator is one such example).
>
> The questions I have are:
> 1) Will the VIC definitely ignore these writes (I presume it will not
> address wrap and write to some existing VIC register)
> 2) Will a SuperCPU be able to write to this location (I am guessing that it
> just writes through to all registers which are not its own special CPLD). I
> want this expansion available to those users too. I don't have a SuperCPU
> to check...
> 3) Is there any other expansion which might already use these two registers
> (I think the C65 had some extra registers.... what about the C-1)
>
> Any comments appreciated.
> - Nick
>
> Project Overview:
> * 30pin SIMM based RAM expansion (1Mb, 4Mb, 16Mb)
> * Hidden refresh scheme
> * Common memory approach similar to C256 of Transactor design
> * Single board plug-in replacement for VIC (original VIC gets PiggyBacked)
> plus some jumper clips for extra address lines
> * Control registers in VIC I/Ospace
> * All logic integrated into a single CPLD (44pin)
> * Internally addressible - available for VIC graphics and usable by
> external processors also.
Will this project emulating a 17xx REu from Commodore till 16MB?
ciao
Arndt
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