Hallo allemaal,
Bogax:
> I wonder if memory to memory transfers within the expansion memory
> and independent of the CPU (and not limited to the CPU's bus speed
> or width) might be useful, in which case an interrupt would also
> be useful.
Please explain more.
I cannot imagine that you're thinking of more then one transfer during a
clockcycle; this is prevented by the way the onboard DRAM's are refreshed by
the VIC.
And if you're thinking of less then one refresh/cycle: the setup of the IRQ,
handling it etc. take so much time that you end up with gaps of at least big
as the time needed to handle the instructions up to the point you can tweak
to your own routine.
Bogax and Rainer about doubling PHI2:
- My not dividing the 8 MHz signal by four? You only need an RC-network to
synchronise the result with PHI2 but the delay is near to zero. See:
http://home.hccnet.nl/g.baltissen/pccard16.gif parts U39b (74LS393), U32c
(74LS04), R3 and C1. This is just a design, so I don't know if the values
for R and C are correct.
- Why do you need that doubling at all? The dot-clock is only needed to
generate the RAS/CAS signals for the DRAM's (see later). I have been doing
some work on a REU as well: http://home.hccnet.nl/g.baltissen/e_reu.htm What
is missing is that I intend to use two 74ALS573 8-bit latches in the
databus. Using these buffers have two advantages:
- data is always available, so any possible delays won't hurt
- it enables me to perform the SWAP operation in two cycles just like the
original REU
I lost some notes for the above page but IMHO it is possible to perform all
three functions using only PHI2 as master to steer the state machine.
> apply row address
> apply RAS
> apply column address
> apply CAS
> read/write data
> (strobe WR)
> release CAS/RAS
PHI2: ___________________
_____| |____
DOT: ____ ____ ____
| |____| |____| |____
^ ^ ^ ^ ^
| | | | |------- end of RAS, CAS, WE
| | | |------------ CAS
| | |----------------- apply column address and WE
| |---------------------- RAS
|--------------------------- apply row address and data
The above is a rough idea what certainly will work with 120 ns DRAM's. This
from my head and I have no schematics or what ever by hand. But I seem to
remember a SCH where RAS and "applying the column address" happened at the
same time. This can be done due to the natural delays. This would mean one
could even use 150 ns DRAM's.
___
/ __|__
/ / |_/ Groetjes, Ruud
\ \__|_\
\___| http://Ruud.C64.org
----- Original Message -----
From: john/lori <henk@access1.net>
To: <cbm-hackers@cling.gu.se>
Sent: Wednesday, August 22, 2001 4:12 PM
Subject: Re: 16 MB REU clone
> > I was thinking of a somewhat simplified design. First of all, I'd omit
> > the "interrupt after transfer" feature, since it is pretty useless.
When
> > it is enabled, the CPU will be interrupted right after the write command
> > (to $df01 or $ff00) that initiated the transfer.
>
> If you're just tying to clone the REC, then maybe interrupts aren't
> to useful.
> I wonder if memory to memory transfers within the expansion memory
> and independent of the CPU (and not limited to the CPU's bus speed
> or width) might be useful, in which case an interrupt would also
> be useful.
>
> bogax
>
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