> > apply row address
> > apply RAS
> > apply column address
> > apply CAS
> > read/write data
> > (strobe WR)
> > release CAS/RAS
>
> PHI2: ___________________
> _____| |____
>
>
> DOT: ____ ____ ____
> | |____| |____| |____
> ^ ^ ^ ^ ^
> | | | | |------- end of RAS, CAS, WE
> | | | |------------ CAS
> | | |----------------- apply column address and WE
> | |---------------------- RAS
> |--------------------------- apply row address and data
>
> The above is a rough idea what certainly will work with 120 ns DRAM's. This
> from my head and I have no schematics or what ever by hand. But I seem to
> remember a SCH where RAS and "applying the column address" happened at the
> same time. This can be done due to the natural delays. This would mean one
> could even use 150 ns DRAM's.
>
That's what I meant, except that you've shown either a 4Mhz dot clock,
or a 2Mhz phi2.
re using 74LS573s, ie transparent latches, I have wondered if you could
meet the worst case data hold times, especially if they're connected
directly to the data bus, but the strobe goes through a lot of decoding
delays? (I figured to have the latch enable end 1/2 dotclock cycly, or
so, prior to the phi2 edge)
bogax
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