On Sat, 29 Dec 2001 ncoplin@orbeng.com wrote:
> Hi All,
>
> REC Refresh:
> Is anyone aware of the memory refresh scheme employed by the REC chips?
>
> Is it RAS only, CBR, or Hidden? If its either of the later two, has anyone
> considered expansions using 1MB chips.
At a (relatively educated) guess, it's RAS only, but that wouldn't stop
you extending the refreshing scheme to larger chips. As CMD proved with
the gate array and 1Mx4 chips in the 1750XL. You need a state machine
which can detect a RAS only refresh cycle and generate an extra refresh
address (or two) based on clocking a counter with the top bit of the
existing refresh counter.
> VDC Refresh:
> Apparantly, register 36 in the VDC controls refresh rate. Has anyone
> experimented to see if increasing the refresh rate will allow larger memory
> chips to be used? Does anyone know the size of the refresh counter or
> whether a CBR or hidden refresh scheme is used for these chips. Given they
> could have been 4464 chips, the newer schemes were know about at the time of
> the design.
8 bit refresh counter, as on VIC-II and the REC. This works for DRAM chips
up to 256Kbit density (41256, 41464). Again, it's the length of the
refresh counter which is important.
Richard
Message was sent through the cbm-hackers mailing list
Archive generated by hypermail 2.1.1.