From: Oliver Achten (achten_at_gmx.de)
Date: 2003-08-18 21:25:44
> No, you will have to do system writes at 1 MHz. Even if the chip
> selects were generated fast enough, the chips themselves need a longer
> write cycle. You can find all the chip timings in the PRG and on
> funet.
Hmm, actually i plan to make it work the following way:
Read/write to the Ram: full 65816 speed (using a 55ns SRAM chip)
Read from Rom: full 65816 speed (using 55ns 29F010 flash Rom)
Access to CIAA,CIAB,SID,VIC,color ram, expansion port: 0.98Mhz access by
synchronizing the 65816 to the standard clock given by the VIC.
Unfortunately i donīt have the equipment to program CPLDs, so iīm going to
build the circuit the old-fashioned way (using 74FXX chips). And yes, the 64er
article gave me the inspiration for this modification, but i actually think
that 2Mhz and nothing more isnīt worth the effort (besides the fact that the
way this guy designed the circuit is very timing critical).
Hmmm, 80ns access time would be too slow for 8.86 Mhz then...
The thing is i just wanted to know these things in advance because i plan to
buy the parts according to the specifications, so that if the PLA cannot
handle 56ns access time, i donīt have to use (more expensive) faster SRAM chips.
But it would be really cool if there would be a solution for the faster
variant...
Besides, of course iīm going to document everything so that in the end, when
everything works, everyone can rebuild this circuit.
So now theres the problem of getting an 65816 CPU. Normal electronic
suppliers here in germany donīt seem to carry it, and the fastest chip i found was a
65C02 @ 4Mhz. But perhaps someone has an idea how to get it?
Thanks, and have a nice day
Oliver
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