From: MagerValp (MagerValp_at_cling.gu.se)
Date: 2003-08-18 22:18:39
>>>>> "OA" == Oliver Achten <achten@gmx.de> writes:
OA> Read/write to the Ram: full 65816 speed (using a 55ns SRAM chip)
OA> Read from Rom: full 65816 speed (using 55ns 29F010 flash Rom)
OA> Access to CIAA,CIAB,SID,VIC,color ram, expansion port: 0.98Mhz
OA> access by synchronizing the 65816 to the standard clock given by
OA> the VIC.
Yep, that works. The SuperCPU solution is pretty elegant - a 1 byte
FIFO so that stores can be done at full speed (from the 65816's
perspective) and it'll only halt if there is already a byte in the
FIFO that hasn't been written.
OA> Unfortunately i donīt have the equipment to program CPLDs, so iīm
OA> going to build the circuit the old-fashioned way (using 74FXX
OA> chips).
All you need is a JTAG cable, which connects to your PC's parallel
port. It's actually quite simple to program CPLD:s, check out Nicolas
Coplin's article that he posted earlier:
http://www.64hdd.com/c64-cpld.html
--
___ . . . . . + . . o
_|___|_ + . + . + . Per Olofsson, arkadspelare
o-o . . . o + MagerValp@cling.gu.se
- + + . http://www.cling.gu.se/~cl3polof/
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