ncoplin_at_orbeng.com
Date: 2003-08-19 09:42:51
Hi Oliver,
The real question is whether you are wanting to build a processor that
accelerates every application, or one that is focussed for BASIC and new
applications.
The former is a very complex design. The latter is potentially simpler as
like what was done with the C64DX, you can leave it up to the programmer to
take into account the 1MHz devices (in the DX case SIDs were still 1MHz
devices)... that is, one must slow the processor manually before reading
from them. Of course, a simple design would assume all writes slowed to 1MHz
hardware. With some complexity it could be mapped as to which writes to do
what.
One of my reasons for getting involve in CPLDs is to understand their
capabilities and to design semi-complex things like the interface for a high
speed 65816 CPU, RAM expansions etc. I don't have plans to get full into it
and create a C1 or GZ processor or anything that complex. Essentially, I
would be interesting in replacing the TTL in this sort of project with a
CPLD.
As it turns out your thinking is very similar to a project I had outlined...
use a fast SRAM chip (from a 486 cache for example), use a second (or
larger) SRAM chip to copy the ROMs to also (important as otherwise the
system will be slowed down to 1MHz) and my clocking plan was to use only the
CPU clock phase, but run it from the DOT clock - hence only 4MHz. But your
idea of a faster clock should also work. My thought was that for simplicity
all writes were slow, synchonised to 1MHz. This would simplify the CPLD, at
the expense of maximum speed (this can be significant if you consider the
use of zero page and stack in some programs).
So on start up the machine runs at 1MHz, copies ROMs to RAM, then switches
clock to high. Patches to the ROM are needed to ensure 1MHz operation for
the disk system, but you may be able to avoid the need for a separate fast
flash chip, especially if you are thinking to use larger RAMs.
If the interfacing design was kept simple, then the project could be use
cheap and simple CPLDs which come in PLCC packaging. These simple chips
however only have a limited number of building blocks. My opinion is if the
design was to be complicated then you would probably have to resort "bigger
chips" which come in TFP144 packages and thus you will be forced to produce
your own precise circuit boards etc.. or expensive adaptors... and may as
well buy a SCPU, 65GZ or C1.
I would be happy to co-operate on such a project, if we could come to an
agreement on how best to support it (send me an email...). But, to be 100%
honest, if the project design needed too many chips more than CPU, SRAM, and
a simple 44pin CPLD (three chips) then it would be far too complex for the
hacker to build and possibly even too expensive. Just my opinion....
You may be able to source some -14 (they do run at 20MHz) 65816 chips
through the www.6502.org website. I have a couple... which I had targetted
for experimenting... The guy there does a once a year subscribed bulk buy,
but was to try and set himself up as a WDC distributor for low volume
samples.
Regards,
Nick
-----Original Message-----
From: Oliver Achten [mailto:achten@gmx.de]
Sent: Tuesday, 19 August 2003 3:26 AM
To: cbm-hackers@cling.gu.se
Subject: Re: Building my monster C64 accelerator
> No, you will have to do system writes at 1 MHz. Even if the chip
> selects were generated fast enough, the chips themselves need a longer
> write cycle. You can find all the chip timings in the PRG and on
> funet.
Hmm, actually i plan to make it work the following way:
Read/write to the Ram: full 65816 speed (using a 55ns SRAM chip)
Read from Rom: full 65816 speed (using 55ns 29F010 flash Rom)
Access to CIAA,CIAB,SID,VIC,color ram, expansion port: 0.98Mhz access by
synchronizing the 65816 to the standard clock given by the VIC.
Unfortunately i donīt have the equipment to program CPLDs, so iīm going to
build the circuit the old-fashioned way (using 74FXX chips). And yes, the
64er
article gave me the inspiration for this modification, but i actually think
that 2Mhz and nothing more isnīt worth the effort (besides the fact that the
way this guy designed the circuit is very timing critical).
Hmmm, 80ns access time would be too slow for 8.86 Mhz then...
The thing is i just wanted to know these things in advance because i plan to
buy the parts according to the specifications, so that if the PLA cannot
handle 56ns access time, i donīt have to use (more expensive) faster SRAM
chips.
But it would be really cool if there would be a solution for the faster
variant...
Besides, of course iīm going to document everything so that in the end, when
everything works, everyone can rebuild this circuit.
So now theres the problem of getting an 65816 CPU. Normal electronic
suppliers here in germany donīt seem to carry it, and the fastest chip i
found was a
65C02 @ 4Mhz. But perhaps someone has an idea how to get it?
Thanks, and have a nice day
Oliver
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