From: Oliver Achten (achten_at_gmx.de)
Date: 2003-08-18 15:37:00
Hi!
I´m new to this list, so i better introduce myself:
My name is Oliver, i´m 22 years old, and a passionate C64 user since 1989.
Since 1 year, i´m currently studying computer science, and my favourite
hobbies are collecting and hacking old consoles/computer systems.
My new project i´m going to realize is building my own 65sc816 based
accelerator modification for my C64. Planned features are:
- 512KB SRAM
- Speed: 8.86Mhz (1/2 * colour clock)
- 128K flash rom for bios, and various c64 operating systems
- 2k eeprom for configuration storage
- possibility to switch back to normal speed via soft and hardware
Now i wonder if my plan to clock it at 8.86Mhz will actually work, because
of the speed of the PLA. Yes, i´m going to integrate a slow-down circuit for
all slow devices in the C64 (VIC, CIA etc..), but i wonder if the PLA will be
fast enough to generate the chip-selects for the system when the clock goes
at 8.86Mhz.
Another "problem" is that the 8.86Mhz will actually be generated ANDing the
0.98Mhz clock with the 17.72Mhz master clock, giving 9 17Mhz cycles when the
CPU can actually access the ram while the VIC is idle. So the pulse-width of
this 8.86Mhz clock will actually be like the 17.72 one ( 56ns ).
Or should i better scrap this idea, and taking the dot clock instead, which
will give me 4 clocks while the VIC is idle, which will result in 3.92Mhz
processing power @ 127ns access time?
Btw, does anyone know where to get 65816 CPU´s in germany?
Have a nice day!
Oliver Achten
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