From: Oliver Achten (achten_at_gmx.de)
Date: 2003-08-19 14:47:31
@Ruud
Hi Ruud! Nice to meet you again here! :-)
> The advantage of the 64'er project was that it worked without the need for
> windows. Slowdown for some windows is still needed but some native C64
> signals can tell a circuit when or when not to activate this slow-down. No
> external programming needed!
> The disadvantage was that the CPU was only used for plm. 50%. With a 14
> Mhz
> 65816 one could run the system on 15 MHz which would end up with a C64
> running on 8 MHz ALL-THE-TIME !!! The critical timing of this design was
> mentioned but that was a point in 1994 (or was it 1992) but not nowadays
> IMHO. The only thing that worries me is the fact that the VIC still can
> claim the bus for quite some ns. after the positive edge of CLK2. This
> means
> that in case of 8, we only can use 7 cycles.
Yeah, that was what i was trying to explain in my first post. The Cpu
actually runs with 17.72Mhz clockcycles, but can actually only use the half of it
(while the VIC is idle) like:
vc = VIC cycle
cx = CPU cycle
vcvcvcvcvcvcvcvcvcc0c1c2c3c4c5c6c7c8vcvcvcvcvcvcvcvcvcc0c1c2c3c4c5c6c7c8
> Keeping things more simple would mean using the systems own DOTCLOCK which
> provides us with 8 MHz and ending up with a 4 MHz C64. Disadvantage: only
> works with a 8 MHz 65xxx which doesn't exist thus forcing one to use a 14
> Mhz 65816 which means waisting CPU-power.
Exactly, but i wanted to deal with this drawback, because the big advantage,
as you say is that it makes the circuit easier. Actually, the original 64er
2Mhz accelerator would also need a 4Mhz part since the designer stuffs 2
cycles into one time-window.
> Remark for Oliver: when using the 65816, what about using its 16 MB
> capabilities? Can provide you with quite some nice ideas.
I´m eager to hear them... :-)
Actually, my ideas were circling around using one 512kb SRAM chip, which
will occupy the lower 3 banking register bits. In Every bank, all register
addresses will appear at the same places, having some kind of 8 virtual C64s.
Switching between the roms, i was thinking about connecting the higher address
lines of the rom to bit 3 - bit 5 of the 65816 banking register, making it
possible of having 64 different Ram/Rom combinations. Perhaps bit 6 could be used
to select full speed/original speed mode, etc....
I hope i mentioned that i planned originally to remove the original drams,
and replacing them completely
with the SRAMs, which is the only way i can think of to modify the system
timing.
@Nick
> The real question is whether you are wanting to build a processor that
> accelerates every application, or one that is focussed for BASIC and new
> applications.
Since this accelerator modifies the whole system timing, all applications
use the faster speed
> The former is a very complex design. The latter is potentially simpler as
> like what was done with the C64DX, you can leave it up to the programmer
> to
> take into account the 1MHz devices (in the DX case SIDs were still 1MHz
> devices)... that is, one must slow the processor manually before reading
> >from them. Of course, a simple design would assume all writes slowed to
> 1MHz
> hardware. With some complexity it could be mapped as to which writes to do
> what.
No need to do that. With the fast SRAM replacing the old DRAMs, everything
(except register writes) can run at full speed.
> One of my reasons for getting involve in CPLDs is to understand their
> capabilities and to design semi-complex things like the interface for a
> high
> speed 65816 CPU, RAM expansions etc. I don't have plans to get full into
> it
> and create a C1 or GZ processor or anything that complex. Essentially, I
> would be interesting in replacing the TTL in this sort of project with a
> CPLD.
Perhaps my TTL design could be some kind of basis for further projects,
including your CPLD ideas.
> As it turns out your thinking is very similar to a project I had
> outlined...
> use a fast SRAM chip (from a 486 cache for example), use a second (or
> larger) SRAM chip to copy the ROMs to also (important as otherwise the
> system will be slowed down to 1MHz) and my clocking plan was to use only
> the
> CPU clock phase, but run it from the DOT clock - hence only 4MHz. But your
> idea of a faster clock should also work. My thought was that for
> simplicity
> all writes were slow, synchonised to 1MHz. This would simplify the CPLD,
> at
> the expense of maximum speed (this can be significant if you consider the
> use of zero page and stack in some programs).
Why slow-down writes when the Drams are replaced anyway? Only access to the
colour ram has to be slowed down.
> If the interfacing design was kept simple, then the project could be use
> cheap and simple CPLDs which come in PLCC packaging. These simple chips
> however only have a limited number of building blocks. My opinion is if
> the
> design was to be complicated then you would probably have to resort
> "bigger
> chips" which come in TFP144 packages and thus you will be forced to
> produce
> your own precise circuit boards etc.. or expensive adaptors... and may as
> well buy a SCPU, 65GZ or C1.
Actually you really wont need much complex logic for the design i intend to
use. In fact, many parts will be simple buffers and latches for the DRAM
emulation for the VIC.
> I would be happy to co-operate on such a project, if we could come to an
> agreement on how best to support it (send me an email...). But, to be 100%
> honest, if the project design needed too many chips more than CPU, SRAM,
> and
> a simple 44pin CPLD (three chips) then it would be far too complex for the
> hacker to build and possibly even too expensive. Just my opinion....
I never intended to make a mass compatible accelerator, just a really simple
and freaked out solution to speed up the C64. But it would be really cool if
my project would start some kind of thinking amongst others (and myself)
about how to make a fast and efficient accelerator, which will, in the end, turn
out much better than my design. :-)
For me, having an accelerated C64 is only a nice side effect. The real gain
for me is the learning effect while i´m building this project (and having
something to impress people... :o) )
Whoa, never thought recieving so much response for this project...
Have a nice day
Oliver
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