From: MagerValp (MagerValp_at_cling.gu.se)
Date: 2003-08-19 15:49:02
>>>>> "OA" == Oliver Achten <achten@gmx.de> writes:
NC> Of course, a simple design would assume all writes slowed to 1MHz
NC> hardware. With some complexity it could be mapped as to which
NC> writes to do what.
OA> No need to do that. With the fast SRAM replacing the old DRAMs,
OA> everything (except register writes) can run at full speed.
[...]
OA> Why slow-down writes when the Drams are replaced anyway? Only
OA> access to the colour ram has to be slowed down.
Unless you replace the PLA, the VIC still reads from internal DRAM,
which has to be written at 1 MHz. If you use a fast SRAM the VIC won't
see what's written to the screen.
--
___ . . . . . + . . o
_|___|_ + . + . + . Per Olofsson, arkadspelare
o-o . . . o + MagerValp@cling.gu.se
- + + . http://www.cling.gu.se/~cl3polof/
Message was sent through the cbm-hackers mailing list
Archive generated by hypermail pre-2.1.8.