> On 2018-01-30, at 18:08, Gerrit Heitsch <gerrit@laosinh.s.bawue.de> wrote: > > R/W must only go LOW while PHI2 is HIGH. That's what that gate setup does. BTW - do we have some timing diagrams showing the relation between various 6502/6510 lines? Among other things this exact case for example. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2018-01-30 18:03:09
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