On 30/01/2018 17:08, Gerrit Heitsch wrote: > Those are RAMs, they don't care if the address bus changes on the fly > during a read cycle. But you don't want that during a write cycle. > Specifically they are static rams, where reads shouldn't be destructive. dram on the other hand have destructive reads and changing the address in the middle of an access will cause data to leak from one row to another (and you end up with similar problems to VSP on the c64). Message was sent through the cbm-hackers mailing listReceived on 2018-01-31 00:01:07
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