On 01/31/2018 12:40 AM, smf wrote: > On 30/01/2018 17:08, Gerrit Heitsch wrote: >> Those are RAMs, they don't care if the address bus changes on the fly >> during a read cycle. But you don't want that during a write cycle. >> > Specifically they are static rams, where reads shouldn't be destructive. > dram on the other hand have destructive reads and changing the address > in the middle of an access will cause data to leak from one row to > another (and you end up with similar problems to VSP on the c64). Yes, but the usual page mode DRAMs have a different control circuit anyway. They only care about the address lines on the HIGH->LOW transitions on /RAS and /CAS (and a few ns later). So you can connect them to the R/W-Line from the 6502 without adding PHI2. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2018-01-31 18:00:02
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