Hello! Jim Brain wrote: > Initial Verilog is there. As always, comments welcome and appreciated. I am not sure I understand this part: (data_opcode[0] ^ address_cpu[0]) You seem to compare whether the lowest bit from the address bus has changed from the previous clock cycle - why? Regards, Michau. Message was sent through the cbm-hackers mailing listReceived on 2018-02-21 10:00:39
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