On 2/21/2018 3:30 AM, Michał Pleban wrote: > Hello! > > Jim Brain wrote: > >> Initial Verilog is there. As always, comments welcome and appreciated. > I am not sure I understand this part: > > (data_opcode[0] ^ address_cpu[0]) > > You seem to compare whether the lowest bit from the address bus has > changed from the previous clock cycle - why? I used the following schematic from Dr. Jefyll as my basis: http://forum.6502.org/viewtopic.php?p=17597&sid=0966e1fa047d491a969a4693b5fed5fd#p17597 His/her explanation: * The XOR gate protects against the false opcode fetch that occurs whenever an interrupt is recognized. There's a risk that a $91 or $B1 opcode will get fetched but not executed. If this happens the circuit mustn't respond. To recognize the beginning of the cpu's interrupt sequence we look for the unique circumstance of the address bus failing to increment in the cycle following an opcode fetch. No increment means the least-significant address line, A0, will fail to toggle. The output of the XOR gate will be low, thus inhibiting the circuit. > > Regards, > Michau. > > > Message was sent through the cbm-hackers mailing list -- Jim Brain brain@jbrain.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2018-02-21 20:00:05
Archive generated by hypermail 2.2.0.