Re: Hardware emulation of 6509 using 6502?

From: Jim Brain <brain_at_jbrain.com>
Date: Sun, 25 Feb 2018 15:24:09 -0600
Message-ID: <a746224a-992e-14ec-75f3-3266e78b9906@jbrain.com>
On 2/25/2018 2:46 PM, Michał Pleban wrote:
> Hello!
>
> Jim Brain wrote:
>
>> The system goes along fine until the CMP $03fa at $f99e.  The 6509 reads
>> $f0, while the 6502 reads $f8.
> This is not a problem. The CPU is reading from uninitalized RAM here, so
> a random value is being read and that's OK. AFAIR, this is a memory
> location containing the "warm start" flag; after initialization, a magic
> value is written there.
Understood, but I find it odd that by changing the CPU only, the number 
differs, and it is *ALWAYS* the same value for the respective CPU.

>
> The real problem is at $F9B9: LDA $97. The code earlier expects the
> value $00 that it has written there, and 6509 indeed reads this value
> back, whereas 6502 reads $97. Therefore the following BMI instruction
> branches back.
>
> You need to figure out why LDA $97 reads back $97 instead of the actual
> value there. A possible reason is that he code has written this value at
> $F9B0: STA $97 - you can see that 6509 writes proper value $00 there,
> but 6502 writes $97.
I *think* the problem is that the 6502 has an internally generated set 
of clocks, while the 6509 expects an external clock.  If I look at the 
6500 datasheet, I see that the PHI1/PHI2 on the 6502 trails the incoming 
PHI0 clock by some amount, but the amount is not defined in the datasheet.

Thus, I think, by feeding the incoming PHI2 clock into the 6502, the 
6502 delays it internally and thus is running "out of sync" with the 
rest of the bus, which is no doubt synchronized with the external PHI2 
clock on the PCB.

Jim

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Received on 2018-02-25 23:00:51

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